In the integrated circuit industry, it is important that integrated circuits be tested in order to ensure that functional integrated circuits are being shipped to customers. Integrated circuits are formed in fabrication facilities by making hundreds to thousands of integrated circuits on a single integrated circuit wafer. Currently, these integrated circuits are diced or cut from the semiconductor wafer and packaged in integrated circuit packages. After being packaged, the integrated circuits are subjected to functional testing and burn-in operations to ensure that each packaged integrated circuit is functioning properly and reliably. A problem with this process is that all of the integrated circuits on the semiconductor wafer that are diced and packaged may not be functioning after final testing. These non-functioning integrated circuits on the wafer are none the less packaged and tested along with functioning integrated circuits on the wafer, incurring additional wasted cost and manufacturing time. It would be advantageous to determine at a wafer level which integrated circuits are functional and non-functional before the time and cost of integrated circuit packaging is incurred.
One method for performing wafer level testing to save time and packaging costs is to form sacrificial wafer level conductive layers on top of the product wafers. These sacrificial test conductive layers are then used to burn-in and test all integrated circuits on an entire wafer prior to dicing or cutting the integrated circuits from the wafer. By performing this wafer level test, integrated circuits which are non-functional can be flagged early in the process and can be discarded without incurring the cost and additional time of the packaging operation.
However, the formation of sacrificial wafer level test layers on top of a product wafer may not be an optimal process. These additional layers added to the top of a product wafer add process complexity to the manufacture of the product wafers. Therefore, these sacrificial wafers may reduce the yield of the product wafer in an unnecessary fashion. Furthermore, the manufacture of semiconductor wafers is performed in the clean room which is substantially free of contamination. On the other hand, testing of the entire wafer is performed in an environment that is substantially unclean. Therefore, once the test operation has been performed in an unclean environment the wafer must be transferred back into a clean environment to perform removal of the sacrificial wafer level test layer. This process of bringing a wafer from a contaminated area into a clean area may result in the clean area ultimately being contaminated whereby other wafers being manufactured in the clean area are going to be impacted in terms of yield.
In addition, the deposition of sacrificial metallic layers on a wafer level scale does not allow one to perform intelligent testing of an integrated circuit. Most of the testing performed by this wafer scale sacrificial deposition is serial in nature and is not intelligent in terms of active circuitry.
Therefore, a need exists for a better method to test integrated circuits on a wafer scale level. This method should maintain the advantages of reducing packaging time and cost for inoperative die while at the same time not damaging or hindering yield of a product wafer.